The generation (technical node) of semiconductor devices has currently advanced through the 90 nm generation, the 64 nm generation, the 45 nm generation, the 32 nm generation and the 22 nm generation node. Further, the 28 nm generation (which is the half-node of the 32 nm generation) has been attracting attention as the design architecture and semiconductor manufacturing technique which is equivalent to the 32 nm generation node. However, although a critical layer to which the strictest design criteria is applied can be manufactured by performing a single exposure in the 32 nm generation, at 28 nm and succeeding generations, because of inherent physical limits which occur by single exposure of a feature, critical layers cannot be manufactured unless double exposure is performed, i.e., the feature must be created by twice exposing the resist, and then etching an underlying hard mask and to be etched layer.
For example, at the 28 nm generation and succeeding generations, the double exposure becomes necessary when forming a hole for a contact plug (hereinafter referred to as a “contact”). However, to reduce manufacturing costs of the semiconductor device, an attempt has been made to manufacture a contact in the 28 nm generation and succeeding generations when performing single exposure by changing the number of contacts or a size of a contact at the time of preparing a photo mask. However, when the single exposure is replaced with the double exposure in this manner, there arises a drawback in that irregular layout dependency is observed in an FET manufactured by the single exposure, and such layout dependency differs from the layout dependency of an FET manufactured by double exposure. In this case, the design and an operation verification result of the FET manufactured by double exposure cannot be utilized by the FET manufactured by single exposure and hence, it is necessary to perform operation verification independent, i.e., different from, the operation verification methodology performed on the FET manufactured by single exposure.
Further, there exists a situation where it is desirable that the same design parameters as the 32 nm generation are used at the 28 nm generation node. However, because the above-mentioned drawback exists, an operational characteristic of an FET of the 28 nm generation manufactured by single exposure becomes different from an operational characteristic of an FET of the 32 nm generation manufactured by single exposure (similar to an operational characteristic of an FET of the 28 nm generation manufactured by double exposure) and hence, the 28 nm generation cannot use the same design parameters as the 32 nm generation. As a result, the design and the operation verification methodology of the FET of the 32 nm generation cannot be utilized by an FET of the 28 nm generation and hence, also in the 28 nm generation, it is necessary for the 28 nm generation to perform the operation verification independently.